1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a system-in-package (SIP) semiconductor apparatus.
2. Related Art
In the semiconductor industry, packaging technology for an integrated circuit has been continuously developed in order to satisfy demands for miniaturization. An example of a packaging technology is the system-in-package (SIP), in which a plurality of semiconductor chips having different functions are sealed in a single package to play a part in a system.
Before memory chips are stacked, one can troubleshoot each memory chip by using normal pins of each chip. However, since a system-in-package includes a controller and stacked memory chips, one must troubleshoot the SIP only through the controller. Thus, it is difficult to accurately determine whether a defect is caused by the controller or the stack of memory chips. Therefore, direct access pins are connected to the memory chips in order to analyze the system-in-package.
FIG. 1 is a diagram schematically illustrating the configuration of a semiconductor apparatus according to the conventional art. The semiconductor apparatus is configured in the form of a system-in-package. In FIG. 1, the system-in-package includes a substrate 10, an interposer 20, a controller 30, and first and second memories 40 and 50. The substrate 10 is provided with first and second access pins 11 and 12 to communicate with an external circuit. The substrate 10 is provided with the first access pins 11 to access the controller 30 in a normal operation, and the second access pins 12 to directly access the first and second memories 40 and 50 in a test operation. The first and second access pins 11 and 12 correspond to external access pins through which the external circuit accesses the semiconductor apparatus. The second access pins 12 particularly correspond to direct access pins through which the external circuit directly accesses the memories 40 and 50, bypassing the controller 30.
The interposer 20 may include interconnections to form connections between the second access pins 12 and the first and second memories 40 and 50, between the first access pins 11 and the controller 30 (not shown), and between the controller 30 and the first and second memories 40 and 50.
The controller 30 is configured to receive external signals, such as commands, addresses, or data signals, which are input through the first access pins 11 in the normal operation. The controller 30 is also configured to transmit the received external signals to the first and second memories 40 and 50 in order to control the first and second memories 40 and 50 by way of transmission/reception circuits provided in the controller 30 and the first and second memories 40 and 50, respectively. Alternatively, the controller 30 may receive signals output from the memories 40 and 50, and output the received signals to an external component through the first access pins 11.
Since the first and second memories 40 and 50 directly receive signals input through the second access pins 12, it is possible to perform a test bypassing controller 30, only if the memories have direct reception bumps 41 and 51 to receive signals input from an external component through the second access pins 12 and the interposer 20. However, the direct reception bumps 41 and 51 increase the sizes of the memories, which is not ideal for miniaturization.